Technical Field
Embodiments described herein are related to the field of integrated circuit implementation, and more particularly to the implementation of clock gating circuits.
Description of the Related Art
Some system-on-a-chip (SoC) designs may utilize high frequency clock signals to maximize the performance capabilities of the SoC. Such high frequency clock signals may, however, contribute to high power consumption. In an attempt to manage power consumption resulting from the use of high frequency clocks, a clock signal coupled to unused or inactive portions of an SoC may be stopped for periods of time. The process of deactivating clock signals for portions of an SoC is commonly referred to as “clock gating.”
The generation of control signals used to activate and deactivate clock signals during clock gating may involve complex logic functions depending on a logical state of the SoC, an operational mode of the SoC, and the like. Transitions of these control signals may require strict adherence to timing requirements to ensure the control signal is asserted and de-asserted before a corresponding transition of the clock signal. Failure to adhere to such timing requirements may result in a clock glitch, i.e., a clock pulse shorter than normal pulses or generate a clock pulse or glitch where none should be present. Such clock glitches may cause unpredictable behavior in a system as some logic gates may interpret the glitch as a normal clock pulse while other logic gates may not, potentially leading to a corruption of state within the system, eventually resulting in a functional failure.
The strict timing requirements of the control signals may restrict the number of logic gates used in the generation of the control signals, thereby limiting the logical complexity of the function used in the generation of the control signals. While employing functions of limited logical complexity may allow for achieving timing requirements for the SoC, the limitation on the number of logic gates may prevent the implementation of control signals for efficient clock gating, thereby providing fewer opportunities for clock gating and power savings.